FIGS. 22 through 25 are sectional views showing the conventional semiconductor packages described in Japanese Patent Laid-Open Publication No. Hei 8-335663. The semiconductor device shown in FIG. 22 is constructed such that electrode pads 504 of an interposer substrate 502 which has a patterned wiring 505 and an insulating film 510 laminated on both surfaces of the patterned wiring 505 are connected to the electrodes of a semiconductor chip 501 via conductors 503. Then, an insulating resin 509 is inserted in between the interposer substrate 502 and the semiconductor chip 501. Subsequently, the interposer substrate 502 is folded from the side surfaces to the rear surface of the semiconductor chip 501, and the insulating resin 509 is applied to an area of the rear surface of the semiconductor chip 501 at which the chip surface is exposed, thereby adhering the interposer substrate 502 to the semiconductor chip 501. This allows for obtaining a small semiconductor package which has generally the same size as that of a bare chip of the semiconductor chip 501. In this semiconductor device, the interposer substrate 502 is adhered to a surface of the semiconductor chip 501 using the insulating resin 509 which serves as an adhesive.
FIG. 23 shows a small three-dimensional semiconductor device which is constructed by stacking the semiconductor device shown in FIG. 22 in layers using solder bumps 507 as a coupling material, and has generally the same size as that of the bare chips.
FIG. 24 is a cross-sectional view showing the above-noted three-dimensional semiconductor devices packaged on a mother board substrate 511.
Additionally, FIG. 25 shows an underfill resin 508 filled around the solder bumps 507 that connect between the mother board substrate 511 of the three-dimensional semiconductor device packaged thereon and the lowermost stage semiconductor device.
FIGS. 26 to 29 are cross-sectional views showing other conventional semiconductor devices described in Japanese Patent Laid-Open Publication No. 2001-196504. The semiconductor device is constructed such that electrode pads 504 of a flexible interposer substrate (flexible substrate) 506 which has a patterned wiring 505 and a thermoplastic insulating resin 512 laminated on both surfaces of the patterned wiring 505 are connected to the electrodes of a semiconductor chip 501 via conductors 503. While being heated, the flexible interposer substrate (flexible substrate) 506 is then bent to be adhered to the side and rear surfaces of the semiconductor chip, thereby forming a small semiconductor package having generally the same size as that of the bare chip.
This semiconductor device is totally different from the one shown in FIG. 22 in using the thermoplastic resin as an insulator for the interposer substrate. Since the interposer substrate 506 itself has an adhesive property and is reduced in elastic modulus when heated, the process of bending the substrate to be adhered to the chip is more simplified than that for the semiconductor device shown in FIG. 22.
On the other hand, FIG. 27 illustrates a small three-dimensional semiconductor device which is constructed by stacking the semiconductor device shown in FIG. 26 in layers using the solder bumps 507 to have generally the same size as that of the bare chips.
FIG. 28 shows the three-dimensional semiconductor device packaged on the mother board substrate 511, and FIG. 29 shows the insulating resin 509 filled in between the lowermost stage semiconductor package and the mother board substrate 511.
By using a thin interposer substrate 502, the semiconductor package shown in FIG. 22 can be formed into a semiconductor package having generally the same size as that of the semiconductor device. Decreasing the package size is effective means for providing an increased packing density, and thus this package structure can be one of the effective means for forming small packages.
Furthermore, this package can be provided with the electrode pad 504 on the front and rear surfaces. Also, outer bumps 1a, 1b can be formed on the pads 504 like as a package shown in FIG. 20, thereby enabling not only planar packaging on a mother board substrate 7 but also three-dimensional packaging thereon by staking packages one on another like as a package shown in FIG. 21. The same semiconductor devices can be packaged in the packaging structure as shown in FIG. 27, thereby enabling high packing density packaging.
However, the conventional semiconductor package has a package structure that can provide a reduced planar packaging area and enables packaging at much higher packing densities through the three-dimensional packaging, but with some limitations. As described above, the same semiconductor devices or semiconductor devices having the same outer dimensions can be formed one on another in the three-dimensional packaging structure as shown in FIG. 27. However, as shown in FIG. 21, for the three-dimensional packaging of semiconductor devices having different outer dimensions, it is desirable for upper stage semiconductor packages 301a, 301b, 301c to have the same dimensions or to be reduced in size with respect to the lowermost stage semiconductor package 301d. This imposes a restriction on the order in which the semiconductor devices can be stacked in layers. The outer bump la serving for connection between packages can be located at the center of the package to provide a higher degree of flexibility to the order of stacking the packages according to their dimensions. However, this is not desirable in terms of ensuring the stability in packaging. It is also conceivable that the outer bump of an upper semiconductor package cannot be accommodated within the dimensions of its lower semiconductor package. Significant increases in number of input/output leads of semiconductor devices may cause the electrode pad of an upper semiconductor device to be placed with difficulty at a connectable area of its smaller lower semiconductor package. Even when this is possible, an extremely fine wiring patter would be required, thus resulting in a very expensive semiconductor package, which is not preferable. This problem with patterning would occur not only in the case where a lower semiconductor package is less in size than the upper semiconductor package but also in some other cases. When a semiconductor device with a large number of input/output leads is redesigned to have a wiring density enough for package-level packaging, such a case would occur in which a relocated electrode pad can not be accommodated within the area of the semiconductor device. This problem would affect the design rule for the interposer substrate responsible for re-patterning of wirings, and thus an out of spec design would have serious effects on manufacturing costs, which is not preferable.
As a solution to address these problems, the package may be conceivably increased in size relative to the semiconductor device. This seems to be against a feature that the package can be made generally in the same size as that of the semiconductor device. However, the package structure shown in FIG. 20 also has a feature that the package can be reduced in thickness. It can be effective means for high density packaging that the package is increased in area up to the necessary but least possible level for three-dimensional packaging of thin packages.
On the other hand, as means for reducing manufacturing costs for semiconductor devices, such a technique is employed in which their outer dimensions are reduced to provide an increased number of devices per wafer. For the semiconductor package shown in FIGS. 20 and 21, such a change in design would require a modification in design of a flexible substrate 101 which has been designed for each of the semiconductor packages 301a, 301b, 301c, and 301d. Furthermore, even when some of the semiconductor devices have been changed, the flexible substrate to be used for the semiconductor package present above or below them need to be changed in design.
Also as a method to address such a problem, packages are desirably standardized in size independent of semiconductor devices, e.g., in a fixed size or by providing the electrode pad at a predetermined location. To this end, such a structure is also desired which allows the package to be greater in size than the semiconductor device.
On the other hand, when a semiconductor device with a large number of input/output leads is re-patterned to have a wiring density enough for package level packaging, a re-patterned electrode pad can be accommodated within the area of the semiconductor device. However, in some cases, the re-patterning of wirings may be performed in a single layer with difficulty. Conventionally, the flexible substrate with an insulating film laminated on both surfaces of a patterned wiring has a patterned wiring portion formed in a single layer. A low wiring density would enable patterning in a single layer. However, when input/output leads are arranged in a grid pattern at an increased wiring density with an increased number of leads allocated to one side of the grid pattern, some patterning arrangements may be or may not be realized. This causes some restrictions to be imposed on the arrangement. It is thus desired a method for addressing these problems to provide a higher degree of flexibility to the flexible substrate to be employed.